The semiconductor memory devices capable of continuously retaining data even if power source is disconnected are widely used in electrical appliances in recent years. The semiconductor memory devices can be classified into a ROM not accepting any program writing, a PROM accepting the program writing while unable to delete programs once written thereinto, an EPROM into which writing is performed electrically and deletion is performed by irradiating ultra-violet ray, and an EEPROM into which both the writing and deletion are performed electrically. A flash memory belongs to the EEPROM, thereby the flash memory can electrically delete all storage data in a core transistor in block.
In the flash memory, writing and deleting operations of charges from a channel section or a source/drain to a floating gate are performed using hot electrons or a Fowler-Nordheim tunneling current. In any of the techniques, voltage application to the floating gate is performed via a control gate on the floating gate. The writing is performed by applying positive voltages to the control gate and relatively low voltages to the drain to thereby store charges from a channel region to the floating gate. Meanwhile, the deletion is performed by applying positive voltages to the source/drain or the channel region using the control gate as a ground to thereby pull out charges from the floating gate. Further, the readout is performed by applying positive voltages to the control gate and relatively low voltages to the drain.
Here, for the semiconductor memory device that includes a flash memory and that its transistor is of the N-type, the source/drain of the core transistor in a memory cell are formed by an ion-implantation of N-type impurities for the drain and by an ion-implantation of N-type impurities at a high concentration after the formation of a source line for the source. Such a formation method is adopted based on the reason described below. In order to improve programming efficiency by generating hot electrons enough required for the writing operation, the drain of the core transistor requires an ion-implantation for example of arsenic with relatively high dose amount (1×1014/cm2 or more) without employing an LDD structure. Meanwhile, however, when the drain is formed by being dosed with impurities at a high concentration, a short-channel effect is concerned about, so that the drain cannot be highly dosed when formed as a source/drain of the transistor used in the general CMOS semiconductor process.
As has been described, when forming the drain in the semiconductor memory device, it is required to perform ion-implantation at a dose amount lower than that for forming the source, causing a problem of higher drain contact resistance. Incidentally and in addition thereto, a PN junction is formed by an ion-implantation of relatively low dose amount, causing another problem that the withstand voltage of the PN junction of the drain is unable to be improved due to a shallow junction by which the transition region of the PN junction is in the vicinity of the substrate surface.
The present invention has been made in view of the above-described problems, and an object thereof is to provide a highly reliable semiconductor memory device and a manufacturing method of the same.